Title :
A class of easily path delay fault testable circuits
Author :
Haniotakis, T. ; Kalligeros, E. ; Nikolos, Dimitris ; Sidiropulos, G. ; Tsiatouhas, Y. ; Vergos, Haridimos T.
Author_Institution :
Dept. of Comput. Eng. & Inf., Patras Univ., Greece
Abstract :
The number of physical paths in a carry save or modified Booth multiplier, as well as in a non-restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists. In this paper we present sufficient modifications of the above mentioned circuits so that a basis consisting of SPP-HFRT paths exists. The cardinality of the derived basis is very small. Also, hardware and delay overheads due to the modifications are respectively small and negligible
Keywords :
carry logic; cellular arrays; delays; design for testability; dividing circuits; integrated circuit testing; logic design; logic testing; multiplying circuits; DFT; SPP-HFRT paths; carry save multiplier; delay-verifiable circuits; hazard-free robustly testable paths; modified Booth multiplier; nonrestoring cellular array divider; path delay fault testable circuits; single path propagating type; Circuit faults; Circuit testing; Electrical fault detection; Hardware; Informatics; Integrated circuit modeling; Manufacturing processes; Physics computing; Propagation delay; Robustness;
Conference_Titel :
Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5975-5
DOI :
10.1109/SSMSD.2000.836466
