A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process

Author

Wada, Atsushi ; Tani, Kuniyuki ; Matsushita, Yoshifumi ; Harada, Yasoo

Author_Institution

Microelectron. Res. Centre, Sanyo Electr. Co. Ltd., Japan

fYear

1998

fDate

13-16 Sep 1998

Firstpage

57

Lastpage

61

Abstract

We have developed a 20 Msample/s 10 b CMOS ADC with a 2.4 V power supply, in 0.35 μm 1-poly 2-Metal ASIC process without a special analog process, which is suitable for embedding in ASICs because of the small area (4.84 mm²) and small power consumption. To realize this ADC we have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. The prototype chip was fabricated and was measured. It shows good linearity of less than ±1 LSB and 28 mW power consumption with 2.4 V at 20 MHz sampling

Keywords

CMOS integrated circuits; analogue-digital conversion; application specific integrated circuits; low-power electronics; 0.35 micron; 10 bit; 2.4 V; 20 MHz; 28 mW; ADC; ASIC process; CMOS; embedding; interstage amplifying pipeline system; linearity; power consumption; residue amplifiers; Application specific integrated circuits; Bandwidth; CMOS process; CMOS technology; Capacitance; Energy consumption; Linearity; Low voltage; Microelectronics; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.722803

Filename

722803