Title :
A sixth-order CMOS sigma-delta modulator
Author :
San, Ho Yoon ; Hasan, S. M Rezaul
Author_Institution :
Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Perak, Malaysia
Abstract :
A sixth-order sigma-delta modulator is presented. Sixth-order noise shaping is achieved though four stage cascaded noise cancellation network. Behavioral simulation shows that cascaded 2-1-1-2, (second order-first order-first order-second order) is very robust and suitable for VLSI implementation. An experimental prototype was fabricated using 2 μm CMOS process by MOSIS. Measurement result shows that the modulator achieved 89 dB (14.8 bit) peak SNR and 92 dB (15.3 bit) dynamic range for 32 kHz bandwidth at a sampling rate of 1.024 MHz which corresponds to an oversampling ratio of 16. The modulator dissipates 79 mW at +/- 3.3 V supply voltage
Keywords :
CMOS integrated circuits; VLSI; cascade networks; circuit simulation; integrated circuit noise; sigma-delta modulation; -3.3 to 3.3 V; 1.024 MHz; 14.8 to 15.3 bit; 2 micron; 32 kHz; 79 mW; CMOS; MOSIS; VLSI implementation; behavioral simulation; cascaded noise cancellation network; dynamic range; noise shaping; oversampling ratio; sampling rate; sixth-order sigma-delta modulator; Bandwidth; CMOS process; Delta-sigma modulation; Dynamic range; Noise cancellation; Noise robustness; Noise shaping; Prototypes; Signal to noise ratio; Very large scale integration;
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-4980-6
DOI :
10.1109/ASIC.1998.722804
