A 0.35 μm CMOS Technology Optimized for Low-Power Applications

A high performance 0.35 μm CMOS technology is presented for low operating voltages. The increased reliability margin at low supply voltages was used to scale the gate oxide thickness and optimize the channel and source/drain junctions profiles. The resulting well controlled short-channel behaviour of the devices was used to obtain low leakage current at low threshold voltages. Good circuit performance was obtained down to very low supply voltages.