DocumentCode
1917958
Title
A 0.35 μm CMOS Technology Optimized for Low-Power Applications
Author
Montree, A.H. ; Lifka, H. ; Meyssen, V.M.H. ; Verhulst, Y.M.G. ; Woerlee, RH
Author_Institution
Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands.
fYear
1994
fDate
11-15 Sept. 1994
Firstpage
187
Lastpage
190
Abstract
A high performance 0.35 μm CMOS technology is presented for low operating voltages. The increased reliability margin at low supply voltages was used to scale the gate oxide thickness and optimize the channel and source/drain junctions profiles. The resulting well controlled short-channel behaviour of the devices was used to obtain low leakage current at low threshold voltages. Good circuit performance was obtained down to very low supply voltages.
Keywords
CMOS technology; Circuit optimization; Laboratories; Leakage current; Low voltage; MOS devices; Power supplies; Silicon; Threshold voltage; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1994. ESSDERC '94. 24th European
Conference_Location
Edinburgh, Scotland
Print_ISBN
0863321579
Type
conf
Filename
5435698
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