DocumentCode :
1917972
Title :
Automated synthesis of a multiple-sequence test generator using 2-D LFSR
Author :
Yuan, Xin ; Chen, Chien-In Heny
Author_Institution :
Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA
fYear :
1998
fDate :
13-16 Sep 1998
Firstpage :
75
Lastpage :
79
Abstract :
Given a set of pre-computed test vectors obtained by an automatic test pattern generation (ATPG) tool for detecting random-pattern-resistant faults or particular hard-to-test faults presented in a circuit under test (CUT), a simple test generator based on a 2D linear feedback shift register (LFSR) structure is presented in this paper to generate a given test, followed by random patterns. Not only generating deterministic test vectors, the synthesized test generator also has a 2-D LFSR structure which generates better random patterns than a conventional LFSR. Experimental results are provided for practical circuits to demonstrate the effectiveness of the scheme. The scheme allows a trade-off between test vector storage and test hardware. A synthesis procedure of designing this test generator is presented
Keywords :
VLSI; automatic test pattern generation; built-in self test; fault diagnosis; integrated circuit testing; logic testing; shift registers; 2D LFSR; automatic test pattern generation; circuit under test; deterministic test vectors; multiple-sequence test generator; pre-computed test vectors; random-pattern-resistant faults; test generator; test hardware; test vector storage; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit synthesis; Circuit testing; Electrical fault detection; Fault detection; Feedback circuits; Test pattern generators; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
ISSN :
1063-0988
Print_ISBN :
0-7803-4980-6
Type :
conf
DOI :
10.1109/ASIC.1998.722807
Filename :
722807
Link To Document :
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