Title :
An Optimized Poly-Buffered LOCOS Process for a 0.35 μm CMOS Technology
Author :
Miéville, J.P. ; Rooyackers, R. ; Deferm, L.
Author_Institution :
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Abstract :
For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this isolation scheme is demonstrated.
Keywords :
Beak; CMOS process; CMOS technology; Design optimization; Etching; Isolation technology; Oxidation; Silicon; Stress; Temperature;
Conference_Titel :
Solid State Device Research Conference, 1994. ESSDERC '94. 24th European
Conference_Location :
Edinburgh, Scotland
