Title :
Resilient SRAM design using BIST-assisted Timing Tracking
Author :
Lai, Ya Chun ; Huang, Shi Yu
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
Abstract :
In this paper, an SRAM design using BIST-assisted timing-tracking (BITT) scheme to improve parametric yield by 76.7% as compared with the traditional timing-tracking method has been presented. This scheme combines reconfigurable delay line, which is tunable by memory BIST, with dummy bitline timing tracking. Consequently, the timing skew due to cell current fluctuations and imbalanced sense amplifiers can both be taken into account so as to provide more flexible timing control for future nanometer technologies.
Keywords :
SRAM chips; built-in self test; logic design; BIST-assisted timing tracking; SRAM design; built-in self test; cell current fluctuation; dummy bitline timing tracking; imbalanced sense amplifier; memory BIST; nanometer technology; parametric yield; reconfigurable delay line; Built-in self-test; CMOS memory circuits; CMOS technology; Circuit testing; Decoding; Delay lines; Operational amplifiers; Random access memory; Timing; Tunable circuits and devices;
Conference_Titel :
Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1656-1
Electronic_ISBN :
1087-4852
DOI :
10.1109/MTDT.2007.4547613
