DocumentCode
1918600
Title
How to survive the verification of the latest generation of automotive system on chip
Author
Laroche, Arnaud ; Kirscher, Jerome
Author_Institution
Infineon Technologies Austria Villach, Austria
fYear
2013
fDate
24-26 Sept. 2013
Firstpage
1
Lastpage
7
Abstract
The new level of integration achieved by the latest generation of automotive power chips pushes the pre-silicon verification challenges a step further. To cope with these challenges, the proven mixed-signal verification methodologies which have hitherto been used successfully have to be extended. The paper introduces newly applied approaches along with verification simulation results of the latest automotive power circuit generation.
Keywords
Accuracy; Automotive engineering; Hardware design languages; Integrated circuit modeling; Load modeling; Sensitivity; System-on-chip; Automotive System On Chip; Multi-Abstraction; Pre-Silicon Venfication; Real Valued Modeling; Spectre; Top Level Simulation; VHDL; Verilog-AMS;
fLanguage
English
Publisher
ieee
Conference_Titel
Specification & Design Languages (FDL), 2013 Forum on
Conference_Location
Paris, France
ISSN
1636-9874
Type
conf
Filename
6646629
Link To Document