DocumentCode
1918609
Title
An enhanced high performance combinational fault simulator using two-way parallelism
Author
Smith, Steven P.
Author_Institution
Microelectron. & Comput. Technol. Corp., Austin, TX, USA
fYear
1989
fDate
2-4 Oct 1989
Firstpage
294
Lastpage
297
Abstract
A combinational fault simulator using two-way parallelism and a number of refinements to reduce memory usage is presented. The results show the approach to be generally superior to the basic parallel patterns single fault propagation (PPSFP) algorithm. One of the refinements, processing to encourage the sharing of fault machine indices by independent faults, appears to require substantially more processing time than it saves during simulation. The remaining preprocessing steps are comparable to those used for basic PPSFP, and are highly justified by their run-time savings. The concept of adjusting the parallelism factor to account for increasingly random-resistant faults seems to work quite well
Keywords
combinatorial circuits; logic CAD; logic testing; combinational fault simulator; parallel patterns single fault propagation; parallelism factor adjustment; preprocessing steps; processing time; random-resistant faults; refinements to reduce memory usage; run-time savings; two-way parallelism; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Concurrent computing; Electrical fault detection; Fault detection; Memory management; Merging; Parallel processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-1971-6
Type
conf
DOI
10.1109/ICCD.1989.63375
Filename
63375
Link To Document