A novel approach for assertion based verification of DDR memory protocols

In this paper, we present an Assertion based functional verification methodology for DDR type memory cores. The methodology is based on formulating DDR pattern properties extracted from JDEC standard which are then translated to synthesizable DDR Type SVA Protocol checkers for HW Emulation Platforms. The protocol checker verifies the validity of command sequences, command Timing, Mode Registers settings, and Initialization sequence when a DDR Type Memory controller is connected to a DDR Memory Core. The checker records command sequences using SVA coverage semantics during run time. The viability and potential of the approach is demonstrated by a case study using LPDDR3 Memory Protocol.