Title : 
Practical design of globally-asynchronous locally-synchronous systems
         
        
            Author : 
Muttersbach, Jens ; Villiger, Thomas ; Fichtner, Wolfgang
         
        
            Author_Institution : 
Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
         
        
        
        
        
        
            Abstract : 
In this paper we describe a complete design methodology for a globally asynchronous on-chip communication network connecting both locally-synchronous and asynchronous modules. Synchronous modules are equipped with asynchronous wrappers which adapt their interfaces to the self-timed environment and prevent metastability. These wrappers are assembled from a concise library of predesigned technology-independent elements and provide high-speed data transfer. We confirmed the validity of our concept by applying it to an ASIC design implementing the Safer crypto-algorithm
         
        
            Keywords : 
asynchronous circuits; logic design; ASIC design; asynchronous; asynchronous wrappers; design methodology; locally-synchronous; metastability; on-chip communication network; Application specific integrated circuits; Clocks; Design methodology; Frequency synchronization; Hip; Joining processes; Laboratories; Metastasis; Read only memory; Very large scale integration;
         
        
        
        
            Conference_Titel : 
Advanced Research in Asynchronous Circuits and Systems, 2000. (ASYNC 2000) Proceedings. Sixth International Symposium on
         
        
            Conference_Location : 
Eilat
         
        
        
            Print_ISBN : 
0-7695-0586-4
         
        
        
            DOI : 
10.1109/ASYNC.2000.836791