Abstract :
SPICE level simulation combined with digital simulation for analog mixed signal verification runs too slowly to allow adequate full-chip SoC verification on a reasonable schedule. SoC verification increasingly requires AMS modeling at the higher levels of abstraction provided by modern integrated analog and digital mixed-signal simulators. One such abstraction uses event-driven techniques, substituting real-valued digital signals representing voltages or currents for the logic signals found in all standard digital HDL simulators. This is commonly known as RN modeling. RN modeling produces the required simulation performance, but it is limited in its applicability and is difficult to do accurately. In this paper, we will describe when it is appropriate and relatively risk-free to use RN modeling, and we will also explain the pitfalls that designers may encounter when using RN modeling techniques and when it is beneficial to move to other mixed signal verification methods. We will present two detailed examples of RN modeling to show the difficulty and limitations of writing and using RN models.
