Automated synthesis of micro-pipelines from behavioral Verilog HDL

This paper presents a compiler from a standard Hardware Description Language (Verilog HDL) to an asynchronous Control Unit and a synchronous Data Path. The Control Unit, specified as a Signal Transition Graph, can be implemented using research-oriented asynchronous synthesis tools. The Data Path, specified using the Synthesizable Subset of Verilog, can be implemented using state-of-the-art commercial synchronous synthesis tools. Our compiler integrates in a fully automated manner source parsing, control/data splitting, managing the design and inserting matched delays for data bundling constraints. It can be used to produce asynchronous designs in an Application Specific Integrated Circuit design style, since the result is a netlist of standard cells ready for physical design. We describe a simple example of compilation and its results, and we discuss some outstanding issues in the domain of asynchronous Control Unit synthesis