A formal verification framework for Bluespec System Verilog

In systems engineering and hardware design, SysML activity diagrams are widely used for modeling and analyzing complex systems. In addition, Bluespec System Verilog gains recently more popularity in hardware synthesis. This paper proposes an efficient formal verification framework to verify the correctness of the systems´ design. First, we verify a system modeled by SysML activity diagrams using PRISM probabilistic symbolic model checker. Then, we present an efficient algorithm that transforms the SysML activity diagrams to an equivalent BlueSpec code. To express easily the proposed algorithm, we formalize both SysML activity diagrams and BlueSpec language. Finally, we demonstrate the effectiveness of our approach by presenting a case study.