Scaling Gate Electrode Thickness for 0.18 μm CMOS Devices

The thickness of a silicided, phosphorous doped, n+ polysilicon gate electrode was varied, 220nm versus 140nm, to determine its impact on device scaling and performance. CMOS devices with physical gate lengths down to 0.15μm were fabricated utilizing a twin well, double level metal, fully planarized CMOS process. Differences in spacer geometry formation which impacted device short channel behavior were observed as a function of polysiliconi thickness. Also affected by polysilicon thickness were gate electrode work function and Gate Oxide Integrity (GOI). Presented in this paper are issues associated with choosing the optimal poly thickness for use in 0.18μm CMOS processing.