Title :
Why SystemVeriog?
Author_Institution :
Elda Technology Ltd Lewes, UK
Abstract :
SystemVerilog is a hardware design and verification language (HDVL) that combines the features of several domain-specific languages for digital hardware design and verification with a general purpose object-oriented programming language. The paper discusses the functional and performance requirements of each domain, and the history of why particular language design choices were made. SystemVerilog is also compared with SystemC and VHDL.
Keywords :
Data structures; Delays; Hardware; Hardware design languages; Logic gates; Object oriented modeling; Registers; HDVL; Verilog; SystemVerilog; domain-specific language;
Conference_Titel :
Specification & Design Languages (FDL), 2013 Forum on
Conference_Location :
Paris, France
