Title :
The improvement of conditional sum adder for low power applications
Author :
Cheng, Kuo-Hsing ; Chiang, Shu-Min ; Cheng, Shun-Wen
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei Hsien, Taiwan
Abstract :
The authors describe a new conditional-sum rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It is shown that about 10% to 25% power-delay product is saved
Keywords :
CMOS logic circuits; adders; digital arithmetic; logic design; low-power electronics; 0.5 micron; conditional sum adder; conditional sum addition rule; high-speed arithmetic systems; low power applications; Adders; Arithmetic; Buildings; CMOS logic circuits; Data processing; Digital circuits; Digital signal processing; Multiplexing; Power dissipation; Voltage;
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-4980-6
DOI :
10.1109/ASIC.1998.722817
