A time multiplexed programmable array for structured ASIC technology

This paper describes the architecture of a time-multiplexed Programmable Array Logic (PLA) designed for structured ASIC technology. Time multiplexing is realized by storing sixteen PLA configurations in on-chip memory. This inactive an-chip memory is distributed around the chip allowing single cycle configuration change and it can be accessed either from off-chip or from internal logic. Functional testing proves that the structure can be used to emulate multiple independent, communicating designs in virtual hardware environment. Implementation results on structured ASIC validated the solution from both area and timing perspective.