DocumentCode
1919988
Title
State-of-art of delay testing
Author
Jing-bo, Shao ; Guang-sheng, Ma ; Xiao-xiao, Liu
Author_Institution
Coll. of Comput. Sci. & Technol., Harbin Eng. Univ.
fYear
2006
fDate
17-19 Nov. 2006
Firstpage
1
Lastpage
4
Abstract
This paper overviews the research work on delay testing, focusing on the diagnosis of delay testing and fault set compaction, and approaches to delay testing are analyzed, pros and cons of each method is discussed, the future efforts of researchers are pointed out
Keywords
circuit analysis computing; computability; fault diagnosis; integrated circuit design; integrated circuit testing; learning (artificial intelligence); logic testing; SAT-based test generation; fault set compaction; machine learning-based test generation; path delay fault testing; Circuit faults; Circuit testing; Compaction; Computer science; Fault diagnosis; Integrated circuit testing; Propagation delay; Space technology; System testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Industrial Design and Conceptual Design, 2006. CAIDCD '06. 7th International Conference on
Conference_Location
Hangzhou
Print_ISBN
1-4244-0683-8
Electronic_ISBN
1-4244-0684-6
Type
conf
DOI
10.1109/CAIDCD.2006.329360
Filename
4127129
Link To Document