Analysis of CMOS differential input to increase ICMR of folded cascode operational amplifier

This paper presents a CMOS latched comparator designed for low power analog to digital conversion application. The circuit consists of a rail-to-rail operational transconductance amplifier followed by a dynamic latch to achieve a fast, high resolution performance at low power. The regenerative latch efficiently reduces the number of gain stage needed and consumes negligibly small static power. The amplifier acts as a preamplifier providing sufficient gain to overcome dynamic offset of dynamic latch. Simulation across process and temperature variation shows the circuit has reliable operation as low as 2.7V in a standard CMOS 0.18μm mixed signal process. The circuit consumes maximum of 111μA typical current. Average delay is 2.25ns and easily operates at 10MHz.