FPGA implementation of 4 samples DWT based on the model of pyramidal structural data coding

Author

Zhang, Zhenxing ; Hu, Jicheng

Author_Institution

C.J. Huang Inst. of Inf. Technol., Wuhan Univ., China

fYear

2004

fDate

14-16 Sept. 2004

Firstpage

819

Lastpage

823

Abstract

In this paper, fast algorithm for discrete wavelet transform is analyzed, a signal processing model based on pyramidal structural data coding is described, and an implementation architecture of 4 samples DWT for both decomposition and reconstruction is proposed, in which we put only one filter into use. With the multiplier reuse method and techniques such as bit-moving, basic operation, by the language VHDL on the platform of MAXPLUSII, FPGA simulation and implementation for this architecture are fulfilled. Numerical experiments show that our result can decompose a four-sample discrete signal sequence and then reconstruct it successfully.

Keywords

discrete wavelet transforms; encoding; field programmable gate arrays; hardware description languages; multiplying circuits; signal processing; FPGA implementation; FPGA simulation; MAXPLUSII; VHDL; basic operation technique; bit-moving technique; discrete wavelet transform; fast algorithm; four-sample discrete signal sequence; multiplier reuse method; pyramidal structural data coding; signal processing model; Algorithm design and analysis; Discrete wavelet transforms; Field programmable gate arrays; Filters; Information technology; Partitioning algorithms; Signal analysis; Signal processing; Signal processing algorithms; Wavelet analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Information Technology, 2004. CIT '04. The Fourth International Conference on

Print_ISBN

0-7695-2216-5

Type

conf

DOI

10.1109/CIT.2004.1357296

Filename

1357296