Title :
Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest
Author_Institution :
AMD, Austin, TX
Abstract :
This paper describes the hardware accelerated crypto sorter design submission for the MEMOCODE 2008 HW/SW co-design contest. The goal was to sort an encrypted database of records partitioning the problem between a PowerPC processor and the dedicated hardware resources available on a Xilinx Virtex II Pro FPGA. A speedup between 24 and 40 was achieved, when compared with the reference software only solution.
Keywords :
cryptography; field programmable gate arrays; hardware-software codesign; logic partitioning; merging; sorting; MEMOCODE 2008 HW/SW co-design contest; PowerPC processor; Xilinx Virtex II Pro FPGA; encrypted database record sorting; hardware accelerated crypto merge sorter design; logic partitioning; Acceleration; Cryptography; Databases; Field programmable gate arrays; Hardware; Indexes; Random access memory; Software algorithms; Sorting; Time factors;
Conference_Titel :
Formal Methods and Models for Co-Design, 2008. MEMOCODE 2008. 6th ACM/IEEE International Conference on
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-2417-7
DOI :
10.1109/MEMCOD.2008.4547705
