Research and implementation of reversible logic synthesis algorithmin digital system

The reversible logic synthesis is one of the important methods in the digital system´s fault testing and investigating area. As the designing and manufacturing technique of vary large scale digital systems fast develops, under current computer conditions, how to rapidly and accurately implement the reversible logic synthesis of a vary large scale digital systems is a knotty problem that the computer aided logic design researchers have been difficult to resolve and can not evade. Based on deeply studying logical synthesis theories, this paper presented an algorithm called iterative intersection of subset, improved reversible logic synthesis algorithm, and made efficiency experiments of the algorithm. The outcome showed that the reversible logic synthesis performance of vary large scale digital systems using iterative intersection algorithm is markedly superior to the traditional logical synthesis algorithm