Title :
Channel Engineering by Heavy Ion Implants
Author :
Skotnicki, T. ; Guérin, L. ; Mathiot, D. ; Gauneau, M. ; Grouillet, A. ; Anterroches, C.D. ; André, E. ; Bouillon, P. ; Haond, M.
Author_Institution :
France Telecom, CNET CNS, BP 98, 38243 Meylan, France.
Abstract :
This paper investigates the suitability and applicability of heavy ion implants (indium for NMOS and arsenic or antimony for PMOS) for better channel profiling in advanced CMOS technologies. Such important technological issues as post-implantation damage, the risk of room-temperature freeze-out, the danger of out-diffusion during oxidation, implantation and diffusion modelling for process optimisation, are analysed. The paper further reports on a successful implementation of indium and arsenic channel implantats into a low voltage/low power CMOS technology and compares electrical performances with a standard (boron/phosphorus) technology.
Keywords :
Boron; CMOS technology; Implants; Indium; Low voltage; MOS devices; Oxidation; Paper technology; Risk analysis; Semiconductor device modeling;
Conference_Titel :
Solid State Device Research Conference, 1994. ESSDERC '94. 24th European
Conference_Location :
Edinburgh, Scotland