DocumentCode
1920859
Title
Analysis of Ultra-Low-Power CMOS with Process and Device Simulation
Author
Schrom, G. ; Liu, D. ; Pichler, Ch. ; Svensson, Ch. ; Selberherr, S.
Author_Institution
Institute for Microelectronics, Technical University Vienna, Gusshausstrasse 27-29, A-1040 Wien, Austria
fYear
1994
fDate
11-15 Sept. 1994
Firstpage
679
Lastpage
682
Abstract
The feasibility and the limitations of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-processing of the simulated IV data. On the basis of simplified modern state-of-the-art processes and special scaling a set of possible ultra-low-power CMOS processes was developed and analyzed for their performance on the gate level.
Keywords
Analytical models; CMOS process; CMOS technology; Capacitance; Energy consumption; Implants; Inverters; Low voltage; Threshold voltage; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1994. ESSDERC '94. 24th European
Conference_Location
Edinburgh, Scotland
Print_ISBN
0863321579
Type
conf
Filename
5435807
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