A configurable array architecture for WSI implementation of neural nets

An array architecture supporting general neural nets is presented; in particular, mapping of layered neural nets is discussed. To achieve the communication density required by neural nets using only a relatively simple switched-bus structure, each firing operation for any individual layer is subdivided into a sequence of phases; the problem of mapping the neural graph onto the array so as to minimize the number of phases is then taken into account. A mapping strategy allowing optimization of this number for the complete interconnection case is presented; modifications allowing the achievement of higher operation speed for the noncomplete case are then outlined. Finally, a strategy allowing the achievement of reconfiguration in the presence of faults, so as to grant defect tolerance is described