Title :
Analysis and experimental results of a CVTL buffer design
Author :
Zhu, Zheng ; Carlson, Bradley S.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Abstract :
We present experimental results for a new CMOS logic family: Critical Voltage Transition Logic (CVTL). It has a different structure and different operating characteristic compared to existing CMOS logic circuit families. Its novel delay propagation characteristic makes it much faster than the conventional CMOS logic gate. Measurements show that the CVTL buffer is four to eight times faster than the static counterpart. Although it consumes more energy, the energy-delay product is significantly smaller compared with a static CMOS buffer
Keywords :
CMOS logic circuits; delays; high-speed integrated circuits; logic design; low-power electronics; CMOS logic family; CVTL buffer design; critical voltage transition logic; delay propagation characteristic; energy-delay product; operating characteristic; CMOS logic circuits; Clocks; Inverters; Logic circuits; Logic design; Propagation delay; Rail to rail outputs; Switches; Switching circuits; Voltage;
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-4980-6
DOI :
10.1109/ASIC.1998.722822
