A proposed tail transistor based SRAM cell

In this paper, we have proposed a write efficient SRAM cell. The write power consumption is reduced compare to the 6T cell due to two extra nMOS tail transistors in the pulldown path of the respective inverter. These two tail transistors avoid the discharging of bitlines. The proposed cell is simulated with the help of the MICROWIND3 using advanced BSIM4 model. The SRAM cell is 1.85X faster and consumes 58% less power than the conventional SRAM cell during write mode. Due to two extra transistors, read power consumption and delay are degraded.