Comparison of Device Architecture´s for 0.18μm MOS Transistors on Very Thin Film SOI Material

CMOS SOI devices, realised on very thin silicon film on SIMOX material, are very attractive for ULSI application. There are many advantages over bulk that have been frequently emphasised in the literature [1]. For sub-quarter micron devices, there are several candidate architectures and device operations, depending on the gate material: - enhancement mode Partially or Fully Depleted devices, for a N⁺ polysilicon gate - accumulation mode device, for a P⁺ polysilicon gate and a N type body - enhancement mode device with a mid-gap gate such as TiN [2]. In this paper, we compare these different architectures to clarify their advantages and potentialities. The work has been performed in a consistent way on 0.18αm NMOS devices, based on numerical simulations. Enhanced transistors have been previously discussed[3], so we will focus the comparison to accumulated ones. An efficient method is proposed to optimise the devices, taking into account the main parasitic effects[4], then the drivabilities are compared.