DocumentCode
1921690
Title
SSDR - Reconfigurable Firewall: Reconfiguration Model Performance
Author
Pereira, Fabio Dacencio ; Ordonez, Edward David Moreno
Author_Institution
Dept. of Electr. Eng., Univ. of Sao Paulo-USP, Sao Paulo
fYear
2008
fDate
26-28 March 2008
Firstpage
253
Lastpage
256
Abstract
There are a number of techniques and pieces of hardware and software aimed at promoting information security. In the present paper it is presented a security system dynamically reconfigurable in FPGAs. SSDR presents a robust architecture, which enables the implementation of specific and general security policies in order to guarantee services such as confidentiality, authenticity, integrity, availability, access control, and information audit. The main purposes of SSDR include guaranteeing a great security level by reaching time performance acceptable to a conventional computer network, besides a greater flexibility in relation to a configuration of functionalities and to the security policies. In this paper it presented the reconfigurable firewall module, highlighting its architecture, functionalities and performance, as well as focusing on the impact on the reconfigurable time according the model of project adopted.
Keywords
authorisation; computer networks; field programmable gate arrays; telecommunication security; FPGA; access control; computer network; information auditing; information security; reconfigurable firewall; reconfiguration model performance; security system dynamically reconfigurable; Access control; Availability; Buffer storage; Computer architecture; Computer security; Field programmable gate arrays; Hardware; Information security; Registers; Robust control;
fLanguage
English
Publisher
ieee
Conference_Titel
Programmable Logic, 2008 4th Southern Conference on
Conference_Location
San Carlos de Bariloche
Print_ISBN
978-1-4244-1992-0
Type
conf
DOI
10.1109/SPL.2008.4547770
Filename
4547770
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