Integration of Innovative Process Modules in a Full 0.35 μm CMOS Process and Circuit Demonstration

0.35 ??m CMOS process modules have been developed with the aim of further validation on 200 mm wafers in industrial environment. Lithography, isolation, device architecture and Chemical Mechanical Polishing (CMP) are discussed. A 3-level metallisation scheme is demonstrated with CMP process and CVD Ti/TiN barriers. Integration of the modules is demonstrated on ULSI circuits.