• DocumentCode
    1922319
  • Title

    An Efficient Run Time Control Flow Errors Detection by DCT Technique

  • Author

    Lai, Hung-Chuan ; Horng, Shi-Jinn ; Fan, Pingzhi ; Wang, Xian ; Pan, Yi

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
  • fYear
    2012
  • fDate
    26-29 March 2012
  • Firstpage
    134
  • Lastpage
    150
  • Abstract
    DCT is usually used in image processing but in this paper we use it to detect the run time control errors. In this paper, using the branch instruction, a program is first divided into several data computing blocks (DCBs), each DCB can then be recognized as an image. To get the signatures of each DCB, we then use one dimension discrete cosine transform (1-DDCT) to compute each DCB to generate the 5-bits relay DCT signature (R-DCT-S) and 32-bits final DCT signature (F-DCT-S).These generated signatures are then embedded into the instruction memory and then used to do the run time error checking. For watchdog, the extra hardware should not reduce the processor performance, not increase the fault detection latency and not increase the memory overhead to store the signatures. As for improving the processor degradation, the whole block error checking is done after the branch instruction, the fault detection latency is improved by checking the intermediate error at the R-type instruction, and the memory overhead is reduced by storing the R-DCT-S to the unused sections of the R-type instruction. The experimental results show that the proposed watchdog gets very high error detection coverage and shortest error detection latency to detect either single fault or multi-faults.
  • Keywords
    digital signatures; discrete cosine transforms; fault diagnosis; microprocessor chips; object detection; object recognition; 32-bits final DCT signature; 5-bits relay DCT signature; DCB signature; DCT technique; R-type instruction; block error checking; branch instruction; data computing block; discrete cosine transform; fault detection latency; image processing; image recognition; instruction memory; memory overhead; processor degradation; processor performance; run time control flow error detection; run time error checking; watchdog processor; Circuit faults; Degradation; Discrete cosine transforms; Hardware; Relays; Software; Transient analysis; control flow check; data computing block (DCB); embedded signature monitoring technique; error detection coverage; error detection latency; fault injection; watchdog processor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Biometrics and Security Technologies (ISBAST), 2012 International Symposium on
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4673-0917-2
  • Type

    conf

  • DOI
    10.1109/ISBAST.2012.18
  • Filename
    6189642