A Micro-FT-UART for Safety-Critical SoC-Based Applications

This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors. The three techniques are triple modular redundancy (TMR), Hamming code and a new technique called correction by parity storing (CPS). An VHDL model of a micro-UART is simulated by the ModelSim v.6.0 and synthesized by the Synopsys Design Compiler v.X-2005.09-SP2. About 1000 single-bit errors and 1000 multiple-bit errors are injected into different parts of the micro-UART to find out the error sensitivity of each specific part. Considering tradeoff between reliability and power consumption, an optimum fault-tolerant technique is assigned to each part to design the micro-FT-UART. This UART corrects all single-bit errors and on average 24% of multiple-bit errors with about 81% power consumption overhead and 152% area overhead.