Study of LDD Implantation Influence on ESD Failure Threshold using Electrothermal Simulation

In CMOS technologies, hardness to ESD events is becoming a major reliability issue. In this context, NMOS transistors are particularly sensible. This study focus on the influence of LDD implantation on ESD failure threshold. ESD tests performed on elementary devices demonstrate the lower performance of LDD transistors. For NMOS transistors with and without LDD, electrothermal simulation have been performed, they lead to results similar to experimental ones, and give an explanation for greater heating in gradual junction.