A High Speed and Low Cost Error Correction Technique for the Carry Select Adder

Author

Namazi, Alireza ; Miremadi, Seyed Ghassem ; Ejlali, Alireza

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran

fYear

2009

fDate

16-19 March 2009

Firstpage

635

Lastpage

640

Abstract

In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error correction technique is compatible with all existing error detection techniques which are proposed for the CSA adder. The synthesized results show that applying this novel error correction technique to a CSA with error detection technique results in up to 18.4%, 3.1% and 14.9%, increase in power consumption, delay and area respectively.

Keywords

adders; carry logic; error correction; fault tolerant computing; carry select adder; embedded processors; error detection technique; high speed error correction technique; low cost error correction technique; power consumption; Adders; Circuit faults; Computer errors; Costs; Delay; Energy consumption; Error correction; Fault detection; Laboratories; Reliability engineering; Carry select adder; Error correction; Error detection; Permanent faults; Transient faults;

fLanguage

English

Publisher

ieee

Conference_Titel

Availability, Reliability and Security, 2009. ARES '09. International Conference on

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-3572-2

Electronic_ISBN

978-0-7695-3564-7

Type

conf

DOI

10.1109/ARES.2009.138

Filename

5066539