New collector design concept for 4.5 kV injection enhanced gate transistor (IEGT)

In this paper, we propose a new collector design concept for high voltage IGBTs/IEGTs, which is composed of a low injection efficiency p-emitter and low transport factor n-buffer. The n-buffer with low transport factor provides decreasing hole injection from p-emitter to n-base to improve the trade-off relation between collector-emitter saturation voltage and turn-off loss. Besides, the n-buffer with low transport factor does not prevent hole injection from p-emitter to n-base at the device turn-on period. As the low transport n-buffer is combined with a low efficiency p-emitter, total switching loss including turn-off loss and turn-on loss decreases. The new collector design concept was applied to 4.5 kV IEGTs, and the fabricated device has demonstrated a reduction of total switching loss by 11% compared with that of the device having only low injection efficiency p-emitter. The fabricated device with the new collector design concept also has excellent turn-off capability.