VLSI design of densely-connected array processors

Paralleled array processors based on cellular neural networks (CNNs) are very useful in high-speed, real-time signal and image processing because of its simplicity for problem mapping and high potential computational bandwidth. Local interconnection and simple synaptic operators are the most attractive features of the cellular neural network (CNN) for VLSI implementation. A computing architecture for CNN processing engine which can be applied for several challenging VLSI hardware design problems, such as CNN accelerator design for heterogeneous computing, is presented. This continuous-time CNN processing engine with digital-programmable synapses and flexible digital interface is designed and prototyped using the current-mode CMOS circuits. A prototyping 5×5 array processor chip is designed and fabricated in 2.0 μm CMOS technology. Measurement results of this prototype chip and its building blocks for array processor design are presented. Experimental results of edge detection operation of this prototype chip are also given