A Parallel Reconfigurable Architecture for Real-Time Stereo Vision

In this paper, a parallel reconfigurable architecture is proposed for real-time stereo vision computation. The architecture is divided into four components: input port, output port, memory and processor. We use task partition methods to achieve the maximum parallel and full pipeline processing of the algorithm implementation. We also adopt memory management to decrease the latency of memory access time and accelerate the processing speed. Data bandwidth control is employed to reduce the hardware resource consumption while maintaining precision demand of computation. Based on the proposed architecture and design method, we have developed a miniature stereo vision machine (MSVM33) to generate high-resolution dense disparity maps at the video rate for real-time applications.