120 V BiC-DMOS process for the latest automotive and display applications

Author

Terashima, Tomohide ; Yamamoto, Fumitoshi ; Hatasako, Kenichi ; Hine, Shiro

Author_Institution

ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan

fYear

2002

fDate

7-7 June 2002

Firstpage

93

Lastpage

96

Abstract

The new 0.5 /spl mu/m design rule 120 V class BiCMOS and DMOS (120 V BiC-DMOS) process is developed by slight modifications from the 90 V BiC-DMOS process. The extra-one mask is added to enforce the isolation. Moreover, all the 5 V 90 V class devices are still included in this process. Improved edge termination structure brings 135 V breakdown voltage and 0.41 /spl Omega/ mm/sup 2/ in DMOS (vertical). DMOS (full isolation type) is also realized by using the RESURF (reduced surface field) structure. The combination of p/sup -/ LDD (lightly doped drain) and rounded P well are used for 120 V PMOS and 120 V field PMOS.

Keywords

BiCMOS integrated circuits; MOS integrated circuits; automotive electronics; display devices; doping profiles; isolation technology; masks; power integrated circuits; semiconductor device breakdown; semiconductor technology; 0.5 micron; 120 V; 135 V; 5 to 90 V; 90 V; BiC-DMOS process; BiCMOS process; DMOS process; HVIC; LDD; RESURF structure; V PMOS; automotive applications; breakdown voltage; display applications; edge termination structure; field PMOS; full isolation DMOS; isolation requirements; lightly doped drain; process mask; reduced surface field structure; rounded P well; submicron design rule process; vertical DMOS; Automotive engineering; BiCMOS integrated circuits; Brightness; Cathode ray tubes; Epitaxial layers; Plasma displays; Power dissipation; Ultra large scale integration; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on

Conference_Location

Sante Fe, NM, USA

Print_ISBN

0-7803-7318-9

Type

conf

DOI

10.1109/ISPSD.2002.1016179

Filename

1016179