Distributed control plane architecture of next generation IP routers

In this paper, we present our research aiming at building a petabit router model for next generation networks. Considering the increasing traffic requirements on the Internet, current gigabit and terabit speed routers will soon not be able to meet user demand. One of the promising trends of router evolution is to build next generation routers with enhanced memory capacity and computing resources, distributed across a very high speed switching fabric. The main limitation of the current routing and signaling software modules, traditionally designed in a centralized manner, is that they do not scale in order to fully exploit such an advanced distributed hardware architecture. This paper discusses an implementation for an control plane for next generation routers integrating several protocol dedicated distributed architectures, aiming at increasing the scalability and resiliency. The proposed architecture distributes the processing functions on router cards, i.e., on both control and line cards. Therefore, it reduces the bottlenecks and improves both the overall performance and the resiliency in the presence of faults. Scalability is estimated with respect to the CPU utilization and memory requirements.