A study on the performance of serial code on shared memory parallel architecture

Author

Sinha, Subrata ; Chakraborty, Subrata ; Barman, Manash Pratim ; Sahu, Aryabarta

Author_Institution

CBS, Dibrugarh Univ., Dibrugarh, India

fYear

2010

fDate

28-30 Oct. 2010

Firstpage

19

Lastpage

22

Abstract

Highly CPU intensive serial task when run on parallel architecture, OS does the Core switching of the given task. Mainly the task is executed by one core at a time, but both the cores are used for processing when core (currently executing) usage reaches 100%. In this scenario OS switches the task between cores. In this paper an attempt has been made to study the time taken to process a segment of serial code along with number of times the task is switched between two cores. Finally linear regression analysis is done on the data to find the influence of core switching on processing time. The study is made on a system having Intel Core 2 Duo with two cores having speed 2.20 GHz and Fedora Core 12.

Keywords

parallel architectures; performance evaluation; regression analysis; shared memory systems; Fedora Core 12; Intel Core 2 Duo; core switching; linear regression analysis; serial code; shared memory parallel architecture; Grid computing; Instruction sets; Parallel architectures; Parallel processing; Switches; Time frequency analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Distributed and Grid Computing (PDGC), 2010 1st International Conference on

Conference_Location

Solan

Print_ISBN

978-1-4244-7675-6

Type

conf

DOI

10.1109/PDGC.2010.5679613

Filename

5679613