DocumentCode :
1925710
Title :
High-voltage UMOSFETs in 4H SiC
Author :
Khan, I.A. ; Cooper, J.A., Jr. ; Capano, M.A. ; Isaacs-Smith, T. ; Williams, J.R.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
2002
fDate :
2002
Firstpage :
157
Lastpage :
160
Abstract :
We report the design and fabrication of UMOSFETs on 4H-SiC with specific on-resistances of 105.1 mΩ cm2 at a current density of 100 A/cm2 and blocking voltage of 5,050 V. These devices incorporate an extended self-aligned p-bottom implant to protect the gate oxide from high electric fields. A novel shadow implant mask was developed to shield the sidewalls from any unwanted p-bottom implant. These UMOSFETs are also the first to incorporate a post-oxidation anneal (POA) in nitric oxide (NO) to improve the inversion layer electron mobility. A single zone JTE (junction termination extension) with peak blocking voltage of 7,500 V was implemented in the device design.
Keywords :
annealing; electron mobility; high field effects; inversion layers; ion implantation; masks; power MOSFET; semiconductor device manufacture; semiconductor device measurement; silicon compounds; wide band gap semiconductors; 4H-SiC high-voltage UMOSFET; 5050 V; 7500 V; NO; SiC; current density; device specific on-resistance; extended self-aligned p-bottom implant; gate oxide protection; high electric fields; inversion layer electron mobility; nitric oxide POA; peak blocking voltage; post-oxidation anneal; shadow implant mask; sidewall shielding; single zone JTE; Annealing; Current density; Electron mobility; Fabrication; Implants; Numerical simulation; Protection; Silicon carbide; Silicon devices; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on
Print_ISBN :
0-7803-7318-9
Type :
conf
DOI :
10.1109/ISPSD.2002.1016195
Filename :
1016195
Link To Document :
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