A novel cold-FET method for determining extrinsic capacitances using a capacitive transmission line model

A novel cold-FET method using a capacitive transmission line (CTL) model to extract extrinsic capacitances for the small-signal equivalent circuit of field-effect transistors (FET´s) is proposed. The extrinsic gate capacitance (C/sub pg/) and drain capacitance (C/sub pd/) of the FET´s are extracted on the basis of the distributed CTL model and ABCD matrix representation for the depletion region beneath gate under the pinched-off cold-FET condition. The extraction method proposed is applied to obtain the small-signal equivalent circuit model for the FET´s. The simulated S parameters using the CTL model exhibit great agreement with the measured S parameters.