DFG-base Dynamic Operation Partitioning for Heterogeneous Multicluster VLIW DSP Processor

The instruction-level parallelism (ILP) of Very Long Instruction (VLIW) Word DSP processor is acquired through operation partitioning and software pipeline. In the previous research of cluster, researchers always focus on reducing move operations between clusters, but rarely consider the effect of heterogeneous architecture combined with SIMD structure and some registers which should be allocated on specified cluster. And the process of building the data flow graph (DFG) has no relationships with the architecture. Therefore, we design an algorithm based on DFG for heterogeneous multicluster VLIW DSP processor to solve the problem. Firstly, using the method of SIMD to find the instructions to be disposed specially. Then the DFG is built with the information of the cluster, and it will be partitioned into several sub-graphs according to the relations among operations. At last the sub-graphs are adjusted with a heuristic method. Experiment results show that this algorithm can make the load of cluster more balanced, and achieve an average of 10% improvement compared to the traditional method.