Title :
A buried p-layer self-aligned process for high-yield LSI circuits
Author :
Sadler, R.A. ; Studtmann, G.D. ; Geissberger, A.E. ; Singh, H.P. ; Burrier, R.A.
Author_Institution :
ITT Gallium Arsenide Technol. Center, Roanoke, VA, USA
Abstract :
To increase the manufacturability of GaAs E/D logic, a 0.7- mu m buried-p-layer (BP) self-aligned gate process was developed. It has demonstrated excellent yields for circuits of up to 5000 gates. Device and circuit performance has been studied as a function of BP implant dose. LSI circuit yield and performance has been characterized using 4-b*4-b, 8-b*8-b, 12-b*12-b, 16-b*16-b, and 20-b*20-b parallel array multipliers on the same die. A high-dose BP implant has resulted in sigma V/sub T/ as low as 8 mV over 3-in wafers, and 20-b*20-b multipliers with self-test yields of 61%. Worst-case multiplication times ranging from 870 ps for the 4-b*4-b to 6.5 ns (68 ps/gate) for the 20-b*20-b multiplier were measured, with all five multipliers showing the fastest room-temperature multiplication times yet reported.<>
Keywords :
III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated circuit technology; integrated logic circuits; large scale integration; multiplying circuits; semiconductor technology; 0.7 micron; 3 in; 4 to 20 bit; 870 to 6500 ps; GaAs; GaAs E/D logic; LSI circuit yield; buried p-layer; circuit performance; enhancement/depletion logic; high-yield LSI circuits; manufacturability; multiplication times; parallel array multipliers; room-temperature; self-aligned gate process; self-test yields; semiconductors; Carrier confinement; Doping; FETs; Gallium arsenide; Implants; Integrated circuit interconnections; Large scale integration; Semiconductor device modeling; Semiconductor process modeling; Threshold voltage;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/GAAS.1989.69330
