Title :
Drain profile engineering of RESURF LDMOS devices for ESD ruggedness
Author :
Parthasarathy, V. ; Khemka, V. ; Zhu, R. ; Whitfield, J. ; Ida, R. ; Bose, A.
Author_Institution :
SmartMOS Technol. Center, Motorola SPS, Mesa, AZ, USA
Abstract :
This paper reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile which eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (It2) of 16 mA/μm has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for medium sized devices without significant compromise in device performance.
Keywords :
doping profiles; electrostatic discharge; leakage currents; power MOSFET; protection; semiconductor device breakdown; semiconductor device measurement; semiconductor device models; semiconductor device reliability; transmission line theory; 100 ns; 20 V; 5 kV; 50 V; ESD protection level; ESD ruggedness; HBM; RESURF LDMOS devices; TLP measurement; deep drain engineered profile; device performance; double RESURF technique; drain profile engineering; electrostatic discharge strikes; filamentation immunity; holding voltage; human body model; maximum second breakdown current; self-protecting lateral power MOSFET structure; snapback; soft leakage degradation; transmission line pulse measurement; Breakdown voltage; Current measurement; Degradation; Electrostatic discharge; Immune system; MOSFET circuits; Power MOSFET; Power engineering and energy; Power transmission lines; Pulse measurements;
Conference_Titel :
Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on
Print_ISBN :
0-7803-7318-9
DOI :
10.1109/ISPSD.2002.1016222