Active pull-down protection for full substrate current isolation in smart power IC´s

Author

Laine, J.P. ; Gonnard, O. ; Charitat, G. ; Bertolini, L. ; Peyre-Lavigne, A.

Author_Institution

LAAS/CNRS, Toulouse, France

fYear

2002

fDate

2002

Firstpage

273

Lastpage

276

Abstract

Substrate current injection, and particularly minority carrier injection, is one of the major causes for redesign in smart power technology. This substrate parasitic current induces unexpected failure system such as latch-up in CMOS circuitry or analog signal perturbation. In this paper, we propose an efficient and compact protection, called active pull-down protection, against this substrate current. It reduces by more than 8 decades the injected current level.

Keywords

CMOS integrated circuits; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; isolation technology; minority carriers; power integrated circuits; protection; CMOS circuitry; active pull-down protection; analog signal perturbation; efficient compact protection; injected current level; latch-up; minority carrier injection; smart power IC; smart power redesign; substrate current; substrate current isolation; substrate parasitic current; unexpected failure system; Bipolar transistors; Bridge circuits; CMOS analog integrated circuits; CMOS technology; Isolation technology; Power integrated circuits; Power system protection; Semiconductor diodes; Substrates; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on

Print_ISBN

0-7803-7318-9

Type

conf

DOI

10.1109/ISPSD.2002.1016224

Filename

1016224