DocumentCode :
1926484
Title :
A wafer-level system integration technology for flexible pseudo-SOC incorporates MEMS-CMOS heterogeneous devices
Author :
Yamada, Hiroshi ; Onozuka, Yutaka ; Iida, Atsuko ; Itaya, Kazuhiko ; Funaki, Hideyuki ; Takahashi, Kazuhiro ; Toshiyoshi, Hiroshi
Author_Institution :
Corp. R&D Center, Toshiba Corp., Kawasaki, Japan
fYear :
2010
fDate :
24-26 Aug. 2010
Firstpage :
1
Lastpage :
4
Abstract :
A flexible pseudo-SoC which integrates electrostatic MEMS and its driver CMOS-LSI for mobile electronics device applications has been developed. From the experiments, the pseudo-SoC process has succeeded to form a fine-pitch on-chip global layer on the MEMS and CMOS-LSI embedded in the epoxy resin and to realize total thickness of 100 μm. This paper reports the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC within the results of a highly-integrated flexible pseudo-SoC incorporating electrostatic MEMS and its driver CMOS-LSI for mobile electronics applications.
Keywords :
CMOS digital integrated circuits; fine-pitch technology; large scale integration; micromechanical devices; resins; system-in-package; system-on-chip; wafer level packaging; MEMS-CMOS heterogeneous devices; SiP; driver CMOS-LSI; electrostatic MEMS; epoxy resin; fine-pitch on-chip global layer; flexible pseudo-SOC process; mobile electronics device; size 100 mum; wafer-level system integration technology; Driver circuits; Electrostatics; Encapsulation; Gratings; Large scale integration; Micromechanical devices; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
CPMT Symposium Japan, 2010 IEEE
Conference_Location :
Tokyo
Print_ISBN :
978-1-4244-7593-3
Type :
conf
DOI :
10.1109/CPMTSYMPJ.2010.5679651
Filename :
5679651
Link To Document :
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