Title :
An experimental high performance 16M DRAM using giga-bit technologies
Author :
Jeong, Gi-Tae ; Cho, Sang-Hyun ; Kim, Min-Jung ; Shin, Yoo-Chul ; Kim, Do-Hyung ; Jang, Seung-Kyu ; Hwang, Bung-Han ; Choi, Dong-Uk ; Ha, Dae-Won ; Kim, Kinam
Author_Institution :
Technology Development, Memory Device Business, Samsung Electronics Co., San #24, Nongseo-Lee, Kiheung-Eup, Yongin-Gun, Kyungki-Do, Korea
Abstract :
An experimental high performance 16M DRAM having 0.18 ¿m design rule for giga bit DRAMs was developed. Junction leakage and junction capacitance was reduced by STI. Fast access time even at low operation voltage(~ 1.5V ) was achieved by TiSi2 gate, W-bit line, Ta2O5 capacitor, and new circuit techniques. Insufficient depth of focus margin for Back-End of Line process was overcome by triple metallization scheme with one W and two Al metals. Owing to these, high speed (Trac= 28 ns at 1.5V ) and small chip size(5.3×5.4 mm2) was achieved.
Keywords :
Capacitors; Circuits; Delay lines; Energy consumption; Leakage current; Low voltage; Metallization; Parasitic capacitance; Random access memory; Technological innovation;
Conference_Titel :
Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
Conference_Location :
Bologna, Italy
