An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog

Author

Ramesh, A.P. ; Tilak, A.V.N. ; Prasad, A.M.

Author_Institution

Sri Vasavi Eng. Coll., Tadepalligudem, India

fYear

2013

fDate

7-9 Jan. 2013

Firstpage

1

Lastpage

5

Abstract

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.

Keywords

field programmable gate arrays; floating point arithmetic; hardware description languages; FP multiplication; FPGA-based high-speed IEEE-754 double-precision floating point multiplier; IEEE-754 format; Verilog; Virtex-6 FPGA; arithmetic operations; floating point multiplication; frequency 414.714 MHz; signal processing computation; Lead; Double precision; FPGA; Floating point; IEEE-754; Multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013 International Conference on

Conference_Location

Tiruvannamalai

Print_ISBN

978-1-4673-5300-7

Type

conf

DOI

10.1109/ICEVENT.2013.6496575

Filename

6496575